Extremely low-voltage charge pump (ELV-CP) and its dedicated multi-stage driver (MS-DRV) for sub-60-mV thermoelectric energy harvesting are proposed. The proposed MS-DRV utilizes the output voltages of each ELV-CP to efficiently boost the control clock signals. The boosted clock signals are used as switching signals for each ELV-CP and MS-DRV to turn switch transistors on and off. Moreover, reset transistors are added to the MS-DRV to ensure an adequate non-overlapping period between switching signals. Measurement results demonstrated that the proposed MS-DRV can generate boosted clock signals of 350 mV from input voltage of 60 mV. The ELV-CP can boost the input voltage of 100 mV with 10.7% peak efficiency. The proposed ELV-CP and MS-DRV can boost the low input voltage of 56 mV.

This paper presents a thin, compact beacon transmitter operating without needing battery replacement by using a photovoltaic (PV) film harvester. The beacon is formed of a power-control circuit (PCC) that can monitor small amounts of power from the harvester and properly control mode switching at low-power consumption. This leads to the realization of a maintenance-free beacon requiring no battery replacement. The beacon prototype is 55×20×2 mm in size and has a PV cell of 3 cm2. It allows a start-up operation from just 44-lux illuminance. The PV area required for the operation can be 1.7 times smaller than that of conventional beacons, thanks to the current saving with appropriate sequential control of the PCC. Since the beacon makes operation possible in emergency stairs, underground passages and other dark places, the application field for Internet of things (IoT) services can be expanded. Furthermore, a beacon equipped with a secondary battery (BSB: Beacon with Secondary Battery) can be configured by adding a charge-discharge power monitoring circuit. The BSB transmits an advertising packet during the daytime while charging surplus power, and works using the stored power during the night; this results in a continuous operation for one week with one transmission every 3 seconds even at 0-lux illuminance. Without developing a new radiofrequency chip or module, commercial low-power devices can be easily adjusted depending on the application by adding appropriate power-control circuits. We are convinced that this design scheme will be effective as a rapid design proposal for IoT services.

Distributed power delivery is blooming in SoC power system because the fine-grained power management needs separate power sources to adjust each voltage island dynamically. In addition, dedicated power sources for critical circuit blocks can achieve better signal integrity. To extensively utilize the power modules when they are redundant and idle, this work applies the cooperation concept in SoC power management. The key controller is a mixed-signal estimator that executes the intelligent procedures, like real-time swap the power module depending on its loading and healthy condition, automatically configure the power system with phase interleaving, and support all the peripheral functions. To demonstrate the proposed concept, a prototype chip for voltage down-conversion is implemented. This chip contains four switched-inductor converter modules to emulate the cooperative power network. Each module is small therefore the power efficiency is not optimal for the heavy load. With the cooperation between power modules, the power efficiency is 88% for 300mA load, that is 8.5% higher than the single module operation.

We propose an energy-efficient real-time scheduling algorithm based on T-L Plane abstraction. The algorithm is designed to exploit Dynamic Power Management and generates a new event called event-s to render longer idle intervals, which increases the chances of switching a processor to the sleep mode. We compare the proposed algorithm with previous work and show that it is effective for energy management.

Nowadays, computer systems are limited by the power and memory wall. As the Dynamic Random Access Memory (DRAM) has dominated the power consumption in modern devices, developing power-saving approaches on DRAM has become more and more important. Among several techniques on different abstract levels, scheduling-based power management policies can be applied to existing memory controllers to reduce power consumption without causing severe performance degradation. Existing power-aware schedulers cluster memory requests into sets, so that the large portion of the DRAM can be switched into the power saving mode; however, only the target addresses are taken into consideration when clustering, while we observe the types (read or write) of requests can play an important role. In this paper, we propose two scheduling-based power management techniques on the DRAM controller: the inter-rank read-write aware clustering approach greatly reduces the active standby power, and the intra-rank read-write aware reordering approach mitigates the performance degradation. The simulation results show that the proposed techniques effectively reduce 75% DRAM power on average. Compared with the existing policy, the power reduction is 10% more on average with comparable or less performance degradation for the proposed techniques.

A novel auto-tuning digital DC--DC converter is presented. In order to reduce the recovery time and undershoot, the auto-tuning control combines LnL, conventional PID and a predictive PID with a configurable predictive coefficient. A switch module is used to select an algorithm from the three control algorithms, according to the difference between the error signal and the two initially predefined thresholds. The detection and control logic is designed for both window delay line ADC and $Sigma Delta$ DPWM to correct the delay deviation. When the output of the converter exceeds the quantization range, the digital output of ADC is set at 0 or 1, and the delay line stops working to reduce power consumption. Theoretical analysis and simulations in the CSMC CMOS 0.5,$mu$m process are carried out to verify the proposed DC--DC converter. It is found that the converter achieves a power efficiency of more than 90% at heavy load, and reduces the recovery time and undershoot.

This paper introduces new FPGA design of user-monitoring system for power management of PC display. From the camera readings the system detects whether the user looks at the screen or not and produces signals to control the display backlight. The system provides over 88% eye detection accuracy at 8f/s image processing rate. We describe new eye-tracking algorithm and hardware and present the results of its experimental evaluation in prototype display power management system.

To manage limited energy resources efficiently, IEEE 802.16e specifies sleep mode operation. Since there can be no communication between the mobile station (MS) and the serving base station (BS) during the unavailability interval, the MS can power down its physical operation components. We propose an improved power saving mechanism (iPSM) which effectively increases the unavailability interval of Type I and Type II power saving classes (PSCs) activated in an MS. After investigating the number of frames in the unavailability interval of each Type II PSC when used with Type I PSC, the iPSM chooses the Type II PSC that yields the maximum number of frames in the unavailability interval. Performance evaluation confirms that the proposed scheme is very effective.

To reduce power consumption of wireless terminals, we have developed ultra-low leakage regulator circuits that control the intermittent terminal operation with very small activity ratio. The regulator circuits supply about 100 mA in the active mode and cut the leakage current to a nanoampere level in the standby mode. The operation of the ultralow-leakage regulator circuits with CMOS/SOI and bulk technologies is described. The leakage-current reduction mechanism in a proposed power switch with bulk technology is explained. Measurement shows that the power switch using reversely biased bulk transistors has a leakage current that is almost as small as that of conventional CMOS/SOI transistor switches.

A mobile station (MS) in an IEEE 802.16e network manages its limited energy using the sleep mode operation. An MS can power down its physical operation components during the unavailability interval of the sleep mode. To reduce energy consumption by increasing the unavailability interval, this paper proposes an enhanced power saving mechanism (ePSM) when both activated Type I and Type II power saving classes (PSCs) exist in an MS. A performance evaluation confirms that ePSM results in the improved performance in terms of the unavailability interval as well as the energy consumption than conventional schemes.

This paper presents a new low-dropout (LDO) regulator with low-quiescent, high-drive and fast-transient performance. This is based on a new composite power transistor composed of a shunt feedback class-AB embedded gain stage and the application of dynamic-biasing schemes to both the error amplifier as well as the composite power transistor. The proposed LDO regulator has been simulated and validated using BSIM3 models and GLOBALFOUNDRIES 0.18-µm CMOS process. The simulation results have shown that the LDO regulator consumes 4.7 µA quiescent current at no load, regulating the output at 1 V from a minimum 1.2 V supply. It is able to deliver up to 450 mA load current with a dropout of 200 mV. It can be stabilized using a 4.7 µF output capacitor with a 0.1 Ω ESR resistor. The maximum transient output voltage is 64.6 mV on the basis of a load step change of 450 mA/10 ns under typical condition. The full load transient response is less than 350 ns.

The design and performance of a sub-nanoampere two-stage power management circuit that uses off-chip capacitors for energy accumulation are presented. Focusing on the leakage current and the transition time of the power switch transistor, we estimated the minimum current for accumulating. On the basis of the results, we devised a two-stage power management architecture for sub-nanoampere operation. The simulated and experimental results for the power management circuit describe the accumulating operation with a 1-nA current source.

This paper describes the design methodology of a low dropout regulator (LDO). It was used to develop a power management sub-system IC for CDMA handsets which is also described in this paper. This IC contains 11 LDOs, bandgap reference, battery charger, control logic and some other peripheral circuits. For CDMA applications, very small ground current in the order of µA in standby mode is required for LDOs. An LDO architecture to meet this requirement and achieve stable operation over the process variation was developed. The on-chip logic efficiently controls all LDOs and battery charger to reduce the power dissipation as much as possible. This mixed signal subsystem has been implemented in the in-house 0.6-µm BCDMOS process. The very low LDO ground current down to 3 µA has been achieved with stable operation.

Dynamic Voltage Scaling (DVS) is a well-known low-power design technique, which adjusts the clock speed and supply voltage dynamically to reduce the energy consumption of real-time systems. Previous studies considered the probabilistic distribution of tasks' workloads to assist DVS in task scheduling. These studies use probability information for intra-task frequency scheduling but do not sufficiently explore the opportunities for the system workload to save more energy. This paper presents a novel DVS algorithm for periodic real-time tasks based on the analysis of the system workload to reduce its power consumption. This algorithm takes full advantage of the probabilistic distribution characteristics of the system workload under priority-driven scheduling such as Earliest-Deadline-First (EDF). Experimental results show that the proposed algorithm reduces processor idle time and spends more busy time in lower-power speeds. The measurement indicates that compared to the relative DVS algorithms, this algorithm saves energy by at least 30% while delivering statistical performance guarantees.

The proposed built-in Power-Cut scheme intended for a wide range of dynamically data retaining memories including embedded SoC memories enables the system-level power management to handle SoC on which the several high density and low voltage scalable memory macros are embedded. This scheme handles the deep standby mode in which the SoC memories keep the stored data in the ultra low standby current, and quick recovery to the normal operation mode and precise power management are realized, in addition to the conventional full power-off mode in which the SoC memories stay in the negligibly low standby current but allow the stored data to disappear. The unique feature of the statically or dynamically changeable internal voltages of memory in the deep standby mode brings about much further reduction of the standby current. This scheme will contribute to the further lowering power of the mobile applications requiring larger memory capacity embedded SoC memories.

This letter proposes a new adaptive power management mechanism (APM2) which takes into account the remaining energy in an IEEE 802.16e system. Benefits of the mechanism are the reduction of frame response delay in a state with sufficient remaining energy, and an increase in the life of a station in a state of insufficient remaining energy. An analytical model for sleep mode operation is developed, and the proposed mechanism is validated by computer simulation.

Many embedded system application in ubiquitous network strongly require the high performance SoC with overcoming the physical limitations in the advanced CMOS. To develop these SoC, the continuous design efforts have been done. The initial efforts are the primitive level circuit technique and power switching control method for suppressing the standby currents. However, the additional physical limitations and system enhancements becomes main factors, the new design efforts have been proposed. These design efforts are the application-oriented technologies from the system level to device level. This paper introduces the self voltage controlled technique to cancel the PVT (process, voltage, and temperature) variation, power distribution and power management for cellular phone application, parallel algorithm and optimized layout DSP, and massively parallel fine-grained SIMD processor for next multimedia application. The high performance SoC for the embedded are achieved by providing the components of the system level IPs and making the application oriented SoC platform.

We demonstrate a fast shutdown and resumption of a logic circuit applied a nonvolatile latch having SrBi2(Ta,Nb)2O9 (SBT) capacitors without a higher drive voltage than a logic voltage of 1.8 V. By assigning an individual drive circuit of the SBT capacitors to the nonvolatile latch not sharing a drive circuit with multiple nonvolatile latches, the fast shutdown and resumption of a logic circuit were completed in 7.5 ns at a drive voltage of 1.3 V. The fast shutdown and resumption without an addition of a high drive voltage to a logic circuit meets a requirement from power-saving applications of system LSIs fabricated in CMOS technologies at 90-nm and below.

In Master-driven TDD based Bluetooth, active Slaves should always listen in the Master-Slave slots because a Slave can transmit packets only after the master polls the Slave. This paper proposes an efficient power management policy to minimize the receiving power which is unnecessarily wasted in Bluetooth. The proposed policy is not controlled by LM (Link manager) protocol, does not need the information about Master-Slave buffers, and guarantees that Slave is in a receive state at Master's polling time. Therefore, there is no degradation of throughput by the proposed policy. The mathematical analysis is carried out in order to investigate our proposed policy. The numerical results show that the proposed policy significantly reduces power consumption over the nave Bluetooth specification.

This paper presents Power-Pro architecture (Programmable Power Management Architecture), a novel processor architecture for power reduction. The Power-Pro architecture has two key functionalities: (i) Supply voltage and clock frequency of a microprocessor can be dynamically varied, and (ii) active datapath width can be dynamically adjusted to the precision of each operation. The most unique point of this architecture is that software programmers can directly specify the requirements of applications such as real-time constraints and precision of the operations. To make programmable power management possible, Power-Pro architecture equips special instructions. Programmers can vary the supply voltage, the clock frequency and the active datapath width dynamically by the instructions. Experimental results show that power consumption for a variety of applications are dramatically reduced by the Power-Pro architecture.